Patrick Lampl

Patrick Lampl completed the bachelor's degree program in "Electronics and Technology Management" as well as the master's degree program
in "Advanced Electronic Engineering" at FH Joanneum and has been active there since 2014 in both teaching and
applied research. In addition, he worked for three years at Silicon Austria Labs (SAL) as a project manager in the
Power Electronics division.

His professional focus is the design of digital circuits for programmable logic devices (FPGAs) as well as
the architecture and programming of processors, especially based on the open RISC-V instruction set architecture.
In addition, he is interested in open-source toolchains for digital design, simulation, and FPGA development.

Another focus lies in higher education teaching and didactics. He successfully completed the University Didactics Training Program (HDW)
and is committed to the practical and methodologically sound teaching of technical content.
In addition, he teaches various courses in both bachelor's and master's degree programs and supervises
project work, bachelor's theses, and master's theses.

Publications

• F. Pöchmüller, P. Lampl and R. Petrella, "Hybrid High-Resolution Digital PWM Based on SERDES & Clock-Phase-Switching Methods," 2026 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, USA, 2026, pp. 1604-1610, doi: 10.1109/APEC51134.2026.11517004.


• V. Chani, P. Lampl, R. Petrella, S. S. Guduguntla and C. Steger, "Accurate Cyclic Synchronization on Bandwidth-Limited Data Links for Hard Paralleling of Power Electronic Converters," 2025 IEEE Energy Conversion Conference Congress and Exposition (ECCE), Philadelphia, PA, USA, 2025, pp. 1-7, doi: 10.1109/ECCE58356.2025.11260329.

R&D Projects

• OBELICS - https://www.fh-joanneum.at/projekt/obelics/


• FIT4BA - https://projekte.ffg.at/projekt/3014958


• JPEC - https://www.fh-joanneum.at/projekt/joanneum-power-electronics-center/


• Various contract projects